1. Field of the Invention
The present invention relates in general to nonvolatile semiconductor storage devices (nonvolatile memories) capable of electrical programming and erase operation and methods of manufacturing the same. More in particular, it relates to a nonvolatile semiconductor storage device having a stacked structure of a silicon oxide film and a silicon nitride film and a method of manufacturing the same.
2. Description of the Related Art
The nonvolatile semiconductor memory devices (nonvolatile memories) having a stacked structure possessing a silicon oxide film on top of a silicon nitride film can roughly classified into two systems: one is a system that uses a non-conductive charge trap film; and the other is a floating gate system that involves accumulating charge in electrically-isolated conductive polycrystalline silicon.
First of all, a nonvolatile memory cell structure using a non-conductive charge trap film will be set forth with reference to FIG. 4. There are formed a semiconductor substrate 401 having a source region 404 and a drain region 405 formed by ion implantation and an insulating film 402 on the channel between these source and drain regions; furthermore a gate electrode 403 made of poly silicon is formed on the insulating film 402. The insulating film 402 is comprised of, in order from the substrate, a bottom silicon oxide film 402a, a silicon nitride film 402b, and a top silicon oxide film 402c. Conventionally, the nonvolatile memory of this type is the Metal-Nitride-Oxide-Silicon (MNOS) type without formation of the top silicon oxide film 402c. Representative examples of products using this structure include IC cards. Programming operation in an MNOS type nonvolatile memory is carried out by applying an appropriate positive voltage to the gate electrode 403 and injected electrons from the channel into the silicon nitride film 402b by direct tunneling through the bottom silicon oxide. At this time, the bottom silicon oxide film 402a has a film thickness of about 2 nm so as to allow direct tunnel phenomena to occur. The erase operation is performed by applying a suitable negative voltage to the gate electrode 403 to extract the electrons injected in the silicon nitride film 402b into the side of the substrate 401 directly through direct tunneling phenomena.
In this MNOS type nonvolatile memory, subjecting the surface of the silicon nitride film 402b to dry oxidation or ozone oxidation makes it possible to form an oxide film of as thin as about 2 nm (402c). As a result, the suppression of a leak current flowing from the SiN holding charge to the gate electrode 403 can improve charge trapping attributes, which is disclosed in Japanese Patent No. 3028635. This patent teaches that the dry oxidation method, however, requires heat treatment at a high temperature (900 to 1200° C.), so ozone oxidation is preferable that enables oxidation at a low temperature of about 350° C.
There have recently emerged growing needs for not only applications (IC cards, etc) in which environmental use temperatures are relatively low (100° C. and less), but nonvolatile memories that can have charge trapping attributes at high temperatures (e.g., 150° C.) and high operation speeds (e.g., on-board applications). An oxide film having a thickness of as thick as 4 nm or more placed on the SiN is essential for meeting these needs. As such, attention has been paid to, instead of the conventional MNOS type, the Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type having a thick oxide film (4 nm or more) placed on the SiN. The MONOS has a structure having a silicon oxide film on a silicon nitride film. Thus, the operation mode is quite different from the above MNOS type. For increased speed, programming is carried out that involves, for example, applying 0 V to the source region 404 and applying appropriate positive voltages to the drain region 405 and the gate electrode 403 to have the transistor switched on, and then accumulating hot electrons generated proximate the drain region 405 in the above silicon nitride film 402b. Read is performed that involves detecting a value of drain current flowing into the source region 404 and the drain region 405. In addition, the erase operation is carried out that involves applying an appropriate positive voltage to any of the substrate 401, the source region 404 and the drain region 405, and extracting the electrons accumulated in the above silicon nitride film 402b by use of the Fowler Nordheim (FN) tunnel phenomena. Alternatively, the erase operation is carried out that involves applying 0 V to the drain region 405 and applying an appropriate positive voltage to the source region 404, applying an appropriate negative charge to the gate electrode 403, and applying a high electric field to between the source region 404 and the gate electrode 403 to generate hot holes from the source region 404, and then implanting the holes into the above silicon nitride film 402b. In this MONOS type, the thicknesses of the bottom silicon oxide film 402a and the top silicon oxide film 402c are from about 4 to about 6 nm.
In the step of forming the above stacked ONO structure, the formation of the top silicon oxide film 402c has utilize, for example, a wet (external combustion type) oxidation method of the batch system. The method, however, has been shown unsuitable as a fine (e.g., a node of 90 nm or less) semiconductor device forming means, because of high-temperature, long-time processing resulting in a large thermal budget. Accordingly, single wafer type In-Situ-Steam-Generation (ISSG) oxidation (internal combustion pyrogenic oxidation) has gone mainstream that is capable of forming a thick oxide film in a short time and meets a larger aperture of the wafer. ISSG oxidation features the formation of radical oxygen immediately above the wafer. This enables the formation of a thick oxidation film at a high temperature in a short time. Well-known examples thereof include a disclosure of Japanese Patent Laid-open No. 2002-289715.
Next, the structure of a floating gate type nonvolatile memory cell will be described. As shown in FIG. 2, the method of fabricating the conventional floating gate type involves forming a semiconductor substrate 201 having a source region 206 and a drain region 207 formed by ion implantation, and a tunneling silicon oxide film 202 on the channel between these source-drain regions. The method further involves forming a floating gate electrode 203 comprised of poly-silicon thereon, forming an interlayer insulating film 204, and subsequently forming a control gate electrode 205 comprised of poly-silicon. The interlayer insulating film 204 includes a silicon oxide film (O) 204a, a silicon nitride film (N) 204b and a silicon oxide film (O) 204c, i.e., an ONO stacked structure, in order from the substrate. The programming of data in this flowing gate type nonvolatile memory cell involves applying, for example, 0 V to the source region 206, applying an appropriate positive voltage to the drain region 207, and further applying an appropriate positive voltage to the control gate electrode 205 to implant the hot electrons generated in the channel into the flowing gate electrode 203. Read is carried out by detecting a value of drain current that passes through the source region and drain region. The erase operation involves applying an appropriate negative voltage to the control gate electrode 205 and applying an appropriate positive voltage to the substrate 201, and then extracting electrons accumulated in the floating gate electrode 203 into the substrate 201 by use of FN tunnel phenomena. In the step of forming the above interlayer insulating film, the formation of the upper layer silicon oxide film 204c conventionally makes use of low pressure CVD, wet oxidation, and the like. A film fabricated by CVD, however, poses the problem of the presence of many electron traps. Wet oxidation requires heat treatment for a long period of time at a high temperature. This apparently presents the problem of forcing a large thermal budget. In addition, Japanese Patent Laid-open No. 5-152288 discloses the degradation of film quality by wet oxidation. The patent describes dry oxidation and ozone oxidation as means without degradation. It also discloses the use of ozone oxidation, which makes it possible to form a relatively thick (2.6 nm) oxide film as compared with the case of dry oxidation (1.1 nm), thereby well suppressing the interlayer leak current.